This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Conventional memory devices have arrays of bit-cells arranged in rows and columns, where each row of bit-cells is accessed via a word line and each column of bit-cells is accessed via one or more bit-lines. Conventional bit-cells tend to leak current into their bit-lines. If the magnitude of the cumulative leakage is too great for a specified number of bit-cells in a column, then the column is typically divided into sub-columns separated by repeater circuits that compensate for the leakage. The use of repeater circuits increases the cost and complexity of memory devices. In addition, the provision of dedicated data write circuitry and data read circuitry for each sub-column further increases the cost and complexity of memory devices.